1. Field of the Invention
The present invention relates in general to the test of semi-conductor memory devices, and more particularly to a test apparatus for a semi-conductor memory device in which data written in a memory cell array and data read therefrom are compared with each other so that a failure of the memory cell array can accurately be checked.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a detailed circuit diagram of a conventional test apparatus for a semi-conductor memory device. As shown in this drawing, the conventional test apparatus comprises a memory section 1 having a plurality of memory cell arrays M11-M14, each of which stores input data Din.
Also, the conventional test apparatus comprises a data discrimination circuit 2 for checking the data stored in the memory cell arrays M11-M14 of the memory section 1 to discriminate a failure thereof, and an output circuit 3 for outputting a fail signal Dout in response to output signals from the data discrimination circuit 2.
The data discrimination circuit 2 includes a NAND gate ND1 for NANDing data AI0-AI3 read from the memory cell arrays M11-M14 in the memory section 1, an OR gate OR1 for ORing the data AI0-AI3 read from the memory cell arrays M11-M14, a NAND gate ND2 for NANDing inverted ones BI0-BI3 of the data AI0-AI3 read from the memory cell arrays M11-M14, an OR gate OR2 for ORing the inverted ones BI0-BI3 of the data AI0-AI3 read from the memory cell arrays M11-M14, a NAND gate ND3 for NANDing output signals from the NAND gate ND1 and the OR gate OR1, and an AND gate AND1 for ANDing output signals from the NAND gate ND2 and the OR gate OR2.
The output circuit 3 includes a pair of NMOS transistors MN1 and MN2. The NMOS transistor MN1 is turned on/off in response to an output signal from the NAND gate ND3. The NMOS transistor MN2 is turned on/off in response to an output signal from the AND gate AND1.
The operation of the conventional test apparatus with the above-mentioned construction will hereinafter be described with reference to FIGS. 1 and 2. FIG. 2 is a view illustrating logical states of the input data Din, the data read from the memory cell arrays M11-M14 in FIG. 1 and the fail signal Dout from the output circuit 3 in FIG. 1.
First, the input data Din is written in parallel into the memory cell arrays M11-M14 in the memory section 1. If the input data Din is logically low, the data AI0-AI3 are read from the memory cell arrays M11-M14 as shown in FIG. 2 and then applied to the data discrimination circuit 2.
In the data discrimination circuit 2, the data AI0-AI3 read from the memory cell arrays M11-M14 are NANDed by the NAND gate ND1 and ORed by the OR gate OR1. If all the data AI0-AI3 read from the memory cell arrays M11-M14 are logically low, the output signal from the NAND gate ND1 is logically high, whereas the output signal from the OR gate OR1 is logically low.
The high output signal from the NAND gate ND1 and the low output signal from the OR gate OR1 are NANDed by the NAND gate ND3, the output signal from which is thus logically high. The high output signal from the NAND gate ND3 is applied to the output circuit 3.
Also, the inverted ones BI0-BI3 of the data AI0-AI3 read from the memory cell arrays M11-M14 are NANDed by the NAND gate ND2 and ORed by the OR gate OR2. All the inverted ones BI0-BI3 of the data AI0-AI3 read from the memory cell arrays M11-M14 are logically high because all the data AI0-AI3 read from the memory cell arrays M11-M14 are logically low. As a result, the output signal from the NAND gate ND2 is logically low, whereas the output signal from the OR gate OR2 is logically high.
The low output signal from the NAND gate ND2 and the high output signal from the OR gate OR2 are ANDed by the AND gate AND1, the output signal from which is thus logically low. The low output signal from the AND gate AND1 is applied to the output circuit 3.
In the output circuit 3, the high output signal from the NAND gate ND3 in the data discrimination circuit 2 is applied to a gate of the NMOS transistor MN1 and the low output signal from the AND gate AND1 in the data discrimination circuit 2 is applied to a gate of the NMOS transistor MN2. As a result, the NMOS transistor MN1 is turned on and the NMOS transistor MN2 is turned off, thereby causing the fail signal Dout from the output circuit 3 to become logically high.
On the other hand, in the case where the input data Din is logically high, all the data AI0-AI2 read from the memory cell arrays M11-MI3 are logically high and the data AI3 read from the memory cell array M14 is logically low, all the inverted ones BI0-BI2 of the data AI0-AI2 read from the memory cell arrays M11-M13 are logically low and the inverted one BI3 of the data AI3 read from the memory cell array M14 is logically high. In this case, in the data discrimination circuit 2, the output signal from the NAND gate ND1 is logically high and the output signal from the OR gate OR1 is logically high. As a result, the output signal from the NAND gate ND3 is logically low. Also, the output signal from the NAND gate ND2 is logically high and the output signal from the OR gate OR2 is logically high. As a result, the output signal from the AND gate AND1 is logically high. Then, the low output signal from the NAND gate ND3 and the high output signal from the AND gate AND1 are applied to the output circuit 3.
Subsequently, in the output circuit 3, the low output signal from the NAND gate ND3 in the data discrimination circuit 2 is applied to the gate of the NMOS transistor MN1 and the high output signal from the AND gate AND1 in the data discrimination circuit 2 is applied to the gate of the NMOS transistor MN2. In response to the low output signal from the NAND gate ND3 and the high output signal from the AND gate AND1, the NMOS transistor MN1 is turned off and the NMOS transistor MN2 is turned on. As a result, the fail signal Dout from the output circuit 3 becomes logically low.
In this manner, the fail signal Dout from the output circuit 3 is outputted as shown in FIG. 2 according to the output data from the memory section 1 and the output signals from the data discrimination circuit 2. The high state of the fail signal Dout from the output circuit 3 means that the memory cell arrays M11-M14 are normally operated. On the contrary, the low state of the fail signal Dout from the output circuit 3 means that the memory cell arrays M11-M14 are abnormally operated.
However, the conventional test apparatus has a disadvantage in that the normal states of the memory cell arrays may be discriminated even when data written in each memory cell array is not the same as that read therefrom. Namely, as shown in FIG. 2, all the data read from the memory cell arrays may be the same even in the case where data written in each memory cell array is not the same as that read therefrom. For this reason, a failure of the memory cell array cannot be discriminated accurately.